# AI Assistant for FPGA Dev

Human page: https://fpga.chat/docs/assistant

Status: Private Alpha — Under Construction.

The AI Assistant for FPGA Dev is the first fpga.chat product line. The first milestone is EDA Error Decoder for Vivado, Quartus, Gowin EDA, Yosys and Verilator logs.

## Use it for

- EDA Error Decoder.
- HDL/RTL review notes for Verilog, SystemVerilog and VHDL.
- Constraints analysis for XDC, SDC, QSF, PCF and CST-style files.
- Board pinout sanity checks when facts are source-backed and board-revision-scoped.
- cocotb and SystemVerilog testbench drafts.
- Open-source checks with Yosys, Verilator, GHDL and Icarus Verilog where appropriate.
- CI/API and VS Code workflow reports later.

## Report contract

Every future engineering report should include:

- confidence;
- evidence;
- sources;
- tool_results;
- warnings;
- limitations;
- repro_steps;
- next_actions.

## Boundary

LLM output is not the source of truth. Generated HDL, constraints and testbenches are drafts unless verified by tool output. fpga.chat does not claim timing, CDC or RDC signoff.