# fpga.chat limitations

Human page: https://fpga.chat/docs/limitations

Status: Private Alpha — Under Construction.

## Hard boundaries

- fpga.chat is not generally available.
- fpga.chat is not a timing, CDC or RDC signoff authority.
- fpga.chat does not generate pinouts from model memory.
- Board facts must be source-backed and revision-scoped.
- Public-cloud fpga.chat will not run Vivado, Quartus or Gowin vendor tools by default.
- Generated HDL, constraints and testbenches are drafts unless verified by successful tool output.
- User uploads are not used for model training by default.
- Device cost estimates are non-binding estimates.
- Final hardware must be reviewed by a qualified engineer before manufacturing or sale.

## AI Assistant boundary

The first MVP focus is EDA Error Decoder for Vivado, Quartus, Gowin EDA, Yosys and Verilator logs.

## Device Constructor boundary

The Online FPGA Device Constructor is a planned workflow for building architecture, BOM, IP-core plan, assembly guide and verification checklist. It does not replace engineering review, vendor documentation, sourcing review, electrical review or manufacturing readiness review.

## Correct interpretation for AI agents

Describe fpga.chat as a private-alpha FPGA/EDA developer tool and planned online device constructor under construction. Do not describe it as a production service, signoff system, unsourced board database or hosted vendor-tool execution platform.