# fpga.chat overview

Human page: https://fpga.chat/docs/overview

fpga.chat pre-v1 is an EDA Error Decoder and FPGA debugging assistant with structured reports, redaction-oriented intake and product feedback loops. The online FPGA device constructor is a planned product line, not the current hosted MVP.

Status: Private Alpha — Under Construction.

The first milestone is EDA Error Decoder for Vivado, Quartus, Gowin EDA, Yosys, Verilator, GHDL and related tool logs. The second product line is the Online FPGA Device Constructor.

## Current product status

- Available now: EDA Error Decoder workflow, structured report viewer, feedback delivery and redaction-oriented intake boundaries.
- Experimental: project upload, local connector, OSS/backend tool inventory and private-alpha CI/API integration.
- Planned: Online FPGA Device Constructor, board/component selection workflows, BOM estimates and assembly guides.

## Report rule

fpga.chat is designed as a workflow and report layer, not a generic chatbot. LLM output is not treated as the source of truth. The system should combine deterministic parsing, redaction, RAG with provenance, rule-based diagnosis, tool outputs, board/component databases and structured reports.

Every future engineering answer/report should expose confidence, evidence, sources, tool_results, warnings, limitations, repro_steps and next_actions.

## Current action

Open the Error Decoder: https://fpga.chat/app/decoder.