{
  "name": "fpga.chat",
  "status": "private_alpha_under_construction",
  "category": "FPGA/EDA Error Decoder and debugging assistant",
  "summary": "fpga.chat pre-v1 is a private-alpha EDA Error Decoder and FPGA debugging assistant with structured reports, VS Code intake, redaction and admin feedback loops. Build is an alpha visual constructor, and Market is a GitHub-hosted core catalog with creator submissions, license review and paid Build usage ledger before automated payouts.",
  "availability": {
    "available_now": [
      "EDA Error Decoder",
      "structured report viewer",
      "VS Code feedback",
      "Email/admin feedback delivery",
      "redaction and retention controls"
    ],
    "experimental": [
      "project upload",
      "local connector",
      "OSS/backend tool inventory",
      "Build visual constructor",
      "Market catalog and creator submission flow",
      "private alpha CI/API integration"
    ],
    "planned": [
      "online FPGA device constructor",
      "board/component selection workflows",
      "BOM and cost estimates",
      "assembly guides"
    ]
  },
  "product_lines": [
    {
      "name": "AI Assistant for FPGA Dev",
      "status": "available_now",
      "scope": [
        "EDA Error Decoder",
        "HDL and project analysis",
        "constraint checks",
        "board-aware guidance",
        "structured reports",
        "CI/API workflow"
      ]
    },
    {
      "name": "Online FPGA Device Constructor",
      "status": "planned",
      "scope": [
        "device idea intake",
        "board and FPGA selection",
        "IP core selection",
        "interface planning",
        "BOM generation",
        "cost estimation",
        "assembly guide",
        "verification checklist"
      ]
    },
    {
      "name": "Market",
      "status": "experimental",
      "scope": [
        "GitHub-hosted FPGA core catalog",
        "authenticated creator submissions",
        "free/open and paid source-available license guidance",
        "Build compatibility review",
        "paid Build usage revenue ledger",
        "AccelFury af metadata intake",
        "moderation before publication"
      ]
    }
  ],
  "planned_supported_tools": [
    "Vivado",
    "Quartus",
    "Gowin EDA",
    "Yosys",
    "Verilator",
    "GHDL",
    "Icarus Verilog",
    "nextpnr"
  ],
  "principles": [
    "LLM is not the source of truth",
    "deterministic parsing",
    "RAG with provenance",
    "evidence-backed reports",
    "structured limitations",
    "no training on user uploads by default"
  ],
  "limitations": [
    "not timing signoff",
    "not CDC/RDC signoff",
    "no unsourced pinout generation",
    "no public-cloud vendor tool execution by default",
    "cost estimates are non-binding",
    "hardware must be reviewed before manufacturing"
  ]
}